Senior Design Verification Engineer (Silicon Design)[Based in Jelutong,Penang]

No. of Headcounts : 3 to 5 headcounts Work Location: Jelutong,Penang

*This is a permanent position that is open to Malaysians citizens or PR holders only

Job Summary: Our Client is a very large international integrated circuit technology

company providing IP/SOC solutions, system customization design solutions, and design

services to customers worldwide.They are in the semiconductor industry and have a global presence. They have established long-term partnerships with top semiconductor design

companies and suppliers, delivering cutting-edge projects and processes from -40nm to 3nm nodes.

As a Senior Design Verification Engineer (Silicon Design), you will play a pivotal role in the verification process of IP, contributing to all stages from testbench development to

regression debugging. Your responsibilities will include developing test plans, implementing verification methodologies, and enhancing efficiency through script

creation. This position requires strong self-drive, excellent communication skills, and adept problem-solving abilities. You will be reporting to the CEO for this position.

KEY ROLE & RESPONSIBILITIES

· Develop and verify new features for IP.

· Build testbenches and create comprehensive test plans.

· Debug regressions and ensure the integrity of verification processes.

· Apply advanced verification methodologies (e.g., UVM, coverage, ASIC design, assertion, randomization) to meet verification goals.

· Develop scripts to streamline verification processes and enhance efficiency.

· Proficiency in design for verification techniques, including assertion-based design strategies, code coverage, and functional coverage.

· Familiarity with PCIE, other IP, or SOC DV.

· Experience with SystemVerilog (SV) and Universal Verification Methodology (UVM).

· Familiar with Linux.

· Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.

· With more than 3 years relevant experience with a Bachelor's degree or more than 2 years with a Master's degree.

· Required candidates who are able to speak in Mandarin & English. Must be fluent in both written and read in English

· Familiar with PCI Express (PCIE)

· Familiar with SystemVerilog(SV) OR Universal Verification Methodology (UVM)

· Familiar with Linux

· Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan,etc)

Working Hours: Monday to Friday 9AM – 6PM (Flexible working Hours/style)

You must be willing to travel whenever required/needed by the company to travel overseas to overseas branches. (CHINA, USA, ETC,)

· Any allowance & benefits can be further discussed upon offer as our client is open for discuss for the overall compensation package when it comes to the offer stage

· Opportunity for career growth and advancement

RM15,000 to RM30,000 per month

Job Type: Permanent

Pay: RM15,000.00 - RM30,000.00 per month

Schedule:

• Day shift
• Monday to Friday

Ability to commute/relocate:

• Jelutong: Reliably commute or planning to relocate before starting work (Preferred)

Application Question(s):

• What is your notice period? (REQUIRED)
• What is your last drawn salary? (REQUIRED)
• What is your expected salary? (REQUIRED)
• Are you Familiar with PCI Express (PCIE) protocols? (please explain)
• Are you Familiar with SystemVerilog(SV) OR Universal Verification Methodology (UVM)?(please explain)
• Are you Familiar with Linux Environment? (please explain)
• Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan)? (please explain)
• Are you fimiliar with other IP, or SOC DV? (please explain)
• Do you have the working experience and knowledge to perform ALL of the following key responsibilities below?

Key Responsibilities:
1. Develop and verify new features for IP.
2. Build testbenches and create comprehensive test plans.
3. Debug regressions and ensure the integrity of verification processes.
4. Apply advanced verification methodologies (e.g., UVM, coverage, ASIC design, assertion, randomization) to meet verification goals.
5. Develop scripts to streamline verification processes and enhance efficiency.