Front End Integration Engineer

Job Description:

• Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
• Responsible for Synthesis, cdc/lint, timing closure, LEC, lower power implementation and netlist quality check with RTL designer and PD team.

Job Requirements:

• Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
• Has Synthesis or physical implementation experience.
• Synthesis, CDC, lint, timing closure, LEC, UPF experience
• Experience with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,VSI/VC-static, Formality, etc…)
• Experience with unix/linux and scripts (tcl, perl, etc.)
• Experience with physical design is a plus.
• Experience with lower power design methodology.
• Good English skills on talking, presentation and writing documents.
• Good communication and strong sense of responsibility, task scheduling, and time management.