Design Verification Engineer

We are seeking a skilled and experienced Design Verification Engineer with a minimum of 6 years of experience in ASIC/FPGA verification. The ideal candidate will have a strong understanding of digital design and verification methodologies, as well as hands-on experience with industry-standard tools and scripting languages. As a Design Verification Engineer, you will collaborate closely with designers and system architects to ensure our designs meet performance, functionality, and reliability goals. Key Responsibilities - Develop comprehensive verification plans based on design specifications. - Design, implement, and execute UVM-based testbenches for functional verification of complex ASIC/FPGA designs. - Write and debug SystemVerilog testbenches to verify RTL at module and chip levels. - Perform functional coverage analysis and implement measures to ensure 100% coverage. - Develop and execute directed tests and randomized test cases to identify design bugs. - Analyze and debug simulation failures, identify root causes, and collaborate with RTL designers for fixes. - Integrate verification environments with industry-standard tools (e.g., Synopsys, Cadence, Mentor Graphics). - Contribute to the definition and improvement of verification methodologies and flows. - Document verification results and provide reports for design reviews. - Participate in code reviews, test coverage reviews, and project meetings. - Collaborate with cross-functional teams to resolve complex design challenges. Requirements - Bachelor’s degree or higher in Electrical/Electronics Engineering, Computer Engineering, or a related field. - Minimum of 6 years of experience in ASIC/FPGA functional verification. - Proficiency in SystemVerilog and UVM methodology. - Strong knowledge of digital design principles and RTL coding (Verilog/VHDL). - Experience with verification tools like QuestaSim, VCS, or Xcelium. - Familiarity with functional coverage, assertion-based verification, and formal verification techniques. - Solid debugging skills using waveform viewers and simulation tools. - Experience with scripting languages like Python, Perl, TCL, or Shell for automation. - Familiarity with industry-standard tools for linting, formal verification, and static timing analysis is a plus. - Strong analytical, problem-solving, and communication skills.