Physical Design Timing Engineer

Job Description - To deliver next generation Intel SoC products with latest process technology and industrial EDA tools. - Responsible for the SoC/Full Chip design verification and closure on physical structural design database. - This includes developing innovative Full Chip methodology and flows to improve the cadence of the SoC design convergence in design domains such as layout, timing, clock tree, formal verification, signal integrity, power routing, bump design, reliability, power and performance. Qualifications - Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent with preferably at least 5 years of industrial experience with solid understanding of physical design integration and industrial verification flows, RTL to GDS hands-on experience on large scale design with advance industrial process node. - Exhibit passions to involve in new design methodology and flow development with scripting such as TCL. Be able to develop scripts from scratch as well as to maintain or enhancing existing codes. - Exhibit excellent soft skills in communication and presentation will add values to enable cross collaborations with different functional teams across Intel. - Physical verification closure of block/sub-system. - Scripts writing for data analysis and recipe creation. Strong analytical ability, problem solving and communication skills. - Ability to work independently and at various levels of abstraction. - Strong communication and team work skills. - Capable of working in a high performing team to deliver the results required from the organization. - Ability to work well in a team and be productive under aggressive schedules