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Manager, Digital Backend

  • Full Time, onsite
  • Agensi Pekerjaan Talent Trader Malaysia Sdn Bhd
  • Kuala Lumpur, Malaysia
RM 16,000 - RM 99,999 / month

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Job Responsibilities: Senior APR/STA engineers oversee digital backend processes from netlist to GDS at both the TOP and block levels. Their tasks include Place & Route (PR), Static Timing Analysis (STA), Physical Verification (PV), Power Analysis (PA), and more. Work closely with digital front-end engineers to troubleshoot issues related to timing, SDC, UPF, etc., and complete moderately complex to advanced Physical Design (PD) tasks at the block or TOP level. Handle pre- and post-mask ECO (Engineering Change Orders). Collaborate with the design team to assess and optimize digital layout efficiency. Job Requirements: Bachelor's degree or higher in Microelectronics or a related field. At least 7 years of experience, with a solid understanding of the full digital backend design flow from netlist to GDS. Proficiency in using one or more design tools such as Innovus/ICC2, PrimeTime (PT), Formality (LEC), StarRC/QRC, PTPX/Volt, and Calibre. Prior experience in successful chip tape-outs with process nodes below 14nm, especially in low-power chip design, is preferred. Experience in TOP-level Place & Route (P&R), including tasks like partitioning, bump assignment, RDL routing, ESD planning, feedthrough insertion, and pin assignment, is advantageous. Hands-on experience with high-speed interfaces such as PCIe and DDR in P&R is a plus.