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Jobs or company...

Design Verification Engineer

Salary undisclosed
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Original
Simplified

Job Description:

  • Responsible for SoC's IP level and SoC level verification.
  • Create verification environment/ testbench using SystemVerilog, UVM and/or System C.
  • Identify and implement functional coverage and SystemVerilog Assertions to catch functional bugs.
  • Develop verification plan for complex digital IP from design spec.
  • Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the DRAM protocol and memory controller microarchitecture.

Requirements:

  • Possess minimum of 3 years experience in digital ASIC/SOC design verification.
  • Strong coding with Verilog and SystemVerilog.
  • Good knowledge of design verification methodology UVM.
  • Experiences with sequence creation, functional cover groups and assertion coding.
  • Familiar with scripting language, such as Perl, C shell, Makefile, Ruby.
  • Understanding on ASIC/SOC design flow.
  • Verify designs for DRAM (e.g., LPDDR4/5, DDR4/5, HBM) protocol compliance.
  • Verifying designs for USB protocol compliance and functionality through rigorous testing and simulation.

Job Description:

  • Responsible for SoC's IP level and SoC level verification.
  • Create verification environment/ testbench using SystemVerilog, UVM and/or System C.
  • Identify and implement functional coverage and SystemVerilog Assertions to catch functional bugs.
  • Develop verification plan for complex digital IP from design spec.
  • Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the DRAM protocol and memory controller microarchitecture.

Requirements:

  • Possess minimum of 3 years experience in digital ASIC/SOC design verification.
  • Strong coding with Verilog and SystemVerilog.
  • Good knowledge of design verification methodology UVM.
  • Experiences with sequence creation, functional cover groups and assertion coding.
  • Familiar with scripting language, such as Perl, C shell, Makefile, Ruby.
  • Understanding on ASIC/SOC design flow.
  • Verify designs for DRAM (e.g., LPDDR4/5, DDR4/5, HBM) protocol compliance.
  • Verifying designs for USB protocol compliance and functionality through rigorous testing and simulation.