Senior Design Verification Engineer (Memory Controller)

Responsibilities Verify designs for DRAM (e.g., LPDDR4/5, DDR4/5, HBM) protocol compliance and functionality through rigorous testing and simulation. Develop and execute design verification plans to ensure functional correctness and compliance with specifications. Perform power-aware simulations and ensure low-power design compliance using UPF (Unified Power Format) standards. Develop and maintain reusable verification environments, including testbenches and test cases, using industry-standard methodologies (e.g., UVM). Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the DRAM protocol and memory controller microarchitecture. Define and implement functional coverage. Perform coverage analysis and identify testing gaps. Required Skills and Qualifications Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field. 4+ years' professional experience in design verification for microprocessor, SoC, memory controller and/or interconnect IP design and verification. Strong understanding of verification methodologies, including UVM or equivalent. Proficiency in hardware description and verification languages, such as SystemVerilog or Verilog. Knowledge of DRAM specification (e.g., LPDDR4/5, DDR4/5, HBM) Experience with UPF (Unified Power Format) for low-power design verification. Experience with Power-aware simulation methodologies. Experience with scripting languages (Python, Perl, etc.) for automation. Knowledge of assertion-based languages such as SystemVerilog Assertions. Excellent problem-solving, debugging, and analytical skills. Strong communication and collaboration skills, with the ability to work effectively in cross-functional teams.