R&D Manager

Job Summary: As a R&D Manager, you will be responsible for leading the architecture, design, layout, and verification for the various IP/ASIC projects of the company including, but not limited to, Serdes PHY standards and Memory Compiler development. Project management will be your responsibility and reporting to you would be the analog design team, digital frontend and backend teams, custom layout team and software team. Responsibilities: • Lead the PHY architecture development for various IP/ASIC projects of the company • Innovate and own System Modeling, Architecture, Design and Development of high performance, low power IO PHY meeting latest USB4 and PCIe 5.0 • Own PHY level Architecture study and recommend system-level design trade-off aligned to IP/SoC requirement and roadmap • Collaborate across functional teams - Logic, Circuit, Verification, Structural Design in PHY level definition meeting Best in Class Power, Performance and Area metrics • Collaborate with SoC integration teams on PHY level requirement and integration issues • Mentor and develop technical leadership Qualifications: • Bachelor's or Master's degree in Electrical Engineering or related field (CGPA 3.50 & above) • 7+ years of experience in analog IC design • Hands-On Experience in high-speed design building blocks for High-Speed Interfaces, SERDES, PLL, CDR, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC • Taped-out in PHY FinFET process • PHY Architecture knowledge needs to span multiple domains (Analog, Digital, Platform Electricals, etc.) • Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, and Architecture specification documentation • Strong problem-solving and analytical skills • Good communication and teamwork skills