
PDK Engineer
Salary undisclosed
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Job Description This position is within the Design Technology Platform (DTP) organization of Technology Development. At Intel, Design Technology Platform and Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on innovative technologies. As part of the Design Technology Platform / Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers. In this role you will be the experienced technical contributor in developing advanced PDK physical verification solution on Intel's process technologies, including but not limited to: (i) Complete breadth coverage across multiple EDA physical verification platforms (Siemens Calibre, Synopsys ICV and Cadence Pegasus). (ii) Continuous advancement of holistic physical verification methodology and solution. (iii) Develop and implement quality assurance workflow in physical verification runset development. (iv) Develop automation supporting runset development. Candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution. Interaction with Process Development Teams, and EDA vendors is expected on a frequent basis in order enable production level verification solutions. #designenablement Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: - Candidate must possess a BS degree with 5+ years of experience or MS degree with 4+ years of experience or PhD degree with 3+ years of experience in Electronics Engineering, Electrical Engineering and Computer Engineering or related field. 3+ years of experience in the following: - DRC/LVS/Antenna/Fill runset development in Calibre-SVRF, ICV-PXL, or Pegasus language. - Develop and implement physical verification runset QA workflow, including testcases development. - Scripting in Python, PERL or TCL. Preferred Qualifications: 3+ years of experience in the following: - PDK development. - IC physical design, layout, and verification flows. - Experienced in PERC verification development. - Knowledge and understanding in advanced process nodes layout design rules implementation. - C++ based EDA tool/software development. - Knowledge of IC manufacturing process flows. - Exposure to CAD/CAE environments involving circuit simulation, physical verification, parasitic extraction, P2P resistance/current density analysis and net listing tools. - Software development practices such as Agile and Test Driven Development.