Associate III - VLSI (Design Verification)
Salary undisclosed
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Role Description
Experience: 4+ years
Working location: Penang, Malaysia
Benefit: Health insurance, flight ticket, work visa, education support for child
Education: Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Key Responsibilities
Cmos,Esd,Dfm
Experience: 4+ years
Working location: Penang, Malaysia
Benefit: Health insurance, flight ticket, work visa, education support for child
Education: Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Key Responsibilities
- Developing test plans
- Coding and bring up of asm, c++ tests
- UVM test bench components coding and maintaining
- Debugging regression fails
- Functional coverage, code coverage closure
- Should have worked on IP level verification
- Hands on experience with UVM, SV, C++
- Experience in developing complex test bench/model in UVM, Verilog, System Verilog
- Hands on experience in developing test plans, coverage closure
- Ability to code readable, maintainable and verifiable code using UVM, SV, C++
- Strong digital design concepts
- Experience in developing asm tests will be an added advantage
- Experience in Power Management, Clock, Reset will be an added advantage
- Experience/Knowledge in processor based systems/sub system/IP Verification will be an added advantage
- Experience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage
Cmos,Esd,Dfm
Role Description
Experience: 4+ years
Working location: Penang, Malaysia
Benefit: Health insurance, flight ticket, work visa, education support for child
Education: Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Key Responsibilities
Cmos,Esd,Dfm
Experience: 4+ years
Working location: Penang, Malaysia
Benefit: Health insurance, flight ticket, work visa, education support for child
Education: Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Key Responsibilities
- Developing test plans
- Coding and bring up of asm, c++ tests
- UVM test bench components coding and maintaining
- Debugging regression fails
- Functional coverage, code coverage closure
- Should have worked on IP level verification
- Hands on experience with UVM, SV, C++
- Experience in developing complex test bench/model in UVM, Verilog, System Verilog
- Hands on experience in developing test plans, coverage closure
- Ability to code readable, maintainable and verifiable code using UVM, SV, C++
- Strong digital design concepts
- Experience in developing asm tests will be an added advantage
- Experience in Power Management, Clock, Reset will be an added advantage
- Experience/Knowledge in processor based systems/sub system/IP Verification will be an added advantage
- Experience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage
Cmos,Esd,Dfm