Senior Engineer

KEY RESPONSIBLITIES: Good to have minimum 5 years of experience in manufacturing, Logistics, Financial domains with jands on testing and verification experiences. Wiling to work in Penang. 1.The scoping includes synthesis, formality check, low power check and full-chip SDC generation. Need work in big and complex with advanced process and technology. 2.Knowledgeable in all aspects of ASIC design flow. 3.Familiar with EDA tools. 4.Good leadership skills. 5.Good teamwork and script skills. 6.Good training skills to ramp-up new team members. RESPONSIBILITIES: 1.Do working assignment for team members, tracking and supporting for critical problems. 2.Co-work with IP/DFT/PD team to improve timing/area/power during synthesize. 3.Netlist quality check including EQV/LowPower/Timing. 4.Generate full-chip level SDC and SDC quality check. EXPERIENCE: 1.Synthesize experience by DC/DC-NXT/Fusion-Compiler. 2.EQV debug experience by FM/LEC. 3.Low power check experience by VC-LP. 4.Static Timing Analysis experience by PT. 5.Power Analysis experience by PTPX. 6.Good at scripts, like Python/perl/Tcl/Shell. Important Note: Candidates applying must be willing to relocate to Penang and must have at least 5 years of experience and/or above.