Senior Verification Engineer

KEY RESPONSIBLITIES: Candidates must have proper experince in testing and verification atleast 5 years minimum experience. Good to have multiple domain experience such as Manufacturing, Logistics, Financial, etc., and willing to work in Penang. 1.Candidate should be able to work independently on various DV task and providing technical guidance to DV team. 2.Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified. 3.Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases. 4.Estimate the time required to write the new feature tests and any required changes to the test environment. 5.Build the directed and random verification tests. 6.Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues. 7.Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements. EXPERIENCE: 1.Proficient in IP/SoC level ASIC verification. 2.Proficient in debugging firmware and RTL code using simulation tools. 3.Proficient in using UVM testbenches and working in Linux and Windows environments. 4.Strong background with UVM, Verilog, System Verilog, C, and C++ . 5.USB,UFS,Ethernet,PCIE,AXI knowledge is a plus. 6.Developing UVM based verification frameworks and testbenches, processes and flows. 7.Automating workflows in a distributed compute environment. Important Note: Candidates applying must be willing to relocate to Penang and must have at least 5 years of experience and/or above.