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Pre- Silicon Design Verification Engineer

Salary undisclosed

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We are looking for a Senior Design Verification Engineer with strong expertise in System Verilog and UVM to lead IP- and SoC-level verification efforts. The ideal candidate should have hands-on experience in verifying high-speed, low-power designs and protocols such as DDR, USB, I2C, SPI, GPIO, and UART. You will be responsible for developing UVM-based testbenches, writing test plans, creating testcases, and driving coverage closure. Strong leadership, problem-solving, and cross-functional collaboration skills are essential. Experience with scripting (Perl, Shell), power-aware simulation, and high-speed interfaces like PCIe, UFS, or Ethernet is highly desirable.