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Pre- Silicon Design Verification Engineer (Junior Executive)

Salary undisclosed

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We are looking for a Junior Design Verification Engineer with 3+ years of experience in ASIC/SoC functional verification. The candidate should be proficient in SystemVerilog and have working knowledge of the UVM methodology. Responsibilities include developing testbenches, writing and executing testcases, and debugging issues in coordination with the design team. Exposure to standard protocols like DDR/LPDDR, HBM, I2C, SPI, UART, and AMBA (AXI/APB) is preferred. Scripting skills (Shell, Perl) and experience with simulation tools and regression environments are a plus.