Sr. Silicon Design Engineer

KEY RESPONSIBILITIES: Collaborate with design team to understand and define verification requirements for high-speed, low power digital circuit designs from definition to implementation. Own and be involved in all aspects of the functional verification from initial test planning, test creation and debug. to coverage and sign-off closure. Own and implement verification of high speed, low power digital designs at IP and System level using both coverage driven constraint random and directed testing techniques as well as formal verification. Implement test benches and components such as test and sequence libraries, monitors, models and BFMs by applying objected oriented programming verification techniques following UVM methodology. PREFERRED EXPERIENCE: Advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. Good understanding and hands-on experience in the UVM concepts and System Verilog language. (SVA, UVM scoreboard) Familiarity with power aware simulation and firmware/hardware co-verification is a plus. Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus. Strong analytical and problem-solving skills with pronounced attention to detail. Scripting language experience: Perl, Ruby, Makefile, shell is a plus. Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality. ACADEMIC CREDENTIALS: Major in EE, CS or related, Master’s Degree with 3+ years or Bachelor’s with 5+ years working experiences.