
Design Verification Engineer
Salary undisclosed
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Key Responsibilities: 1. Develop and verify new features for IP. 2. Build testbenches and create comprehensive test plans. 3. Debug regressions and ensure the integrity of verification processes. 4. Apply advanced verification methodologies (e.g., UVM, coverage, ASIC design, assertion, randomization) to meet verification goals. 5. Develop scripts to streamline verification processes and enhance efficiency. Preferred Experience: 1. Proficiency in design for verification techniques, including assertion-based design strategies, code coverage, and functional coverage. 2. Familiarity with PCIE, other IP, or SOC DV. 3. Experience with SystemVerilog (SV) and Universal Verification Methodology (UVM). 4. Comfortable working in a Linux environment.