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Pre-Silicon RTL Design Engineer (JUNIOR EXECUTIVE)

RM 4,000 - RM 4,999 / month

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We are seeking a Junior RTL Design Engineer with 3+ years of experience in digital logic design using Verilog or SystemVerilog. The role involves working on design quality checks such as Lint, CDC, and basic RTL development for modules like registers and simple control logic. A good understanding of digital design concepts including FIFOs, Arbiters, and Clock Domain Crossing is expected. Familiarity with UPF and timing closure basics is a plus. The candidate should be eager to learn, detail-oriented, and able to contribute effectively within a collaborative design team.