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Pre-Silicon Design Verification Engineer (FRESH LEVEL)

RM 2,500 - RM 2,999 / month

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We are looking for a passionate Entry-Level Design Verification Engineer with up to 3 years of experience and a strong foundation in digital design concepts. The candidate should be proficient in Verilog, SystemVerilog, UVM, and have good programming/scripting skills in C, Python, or similar languages. Responsibilities include assisting in the development of UVM-based testbenches, writing basic testcases, and understanding verification flows. A solid understanding of standard protocols such as AXI, AHB, APB, UART, I2C, SPI, I3C, I2S, and QSPI is expected. The role is ideal for engineers eager to learn, contribute to IP/SOC-level verification, and grow in a dynamic and collaborative environment.