Pre-Silicon RTL Design Engineer (SENIOR EXECUTIVE)

We are looking for an RTL Design Engineer with 5+ years of experience in digital design and a strong understanding of RTL coding using Verilog or SystemVerilog. The candidate should have hands-on experience with design metrics, Lint, CDC/RDC checks, and be familiar with power intent using UPF. A solid understanding of digital building blocks such as FIFOs, Arbiters, DMA, and Clock Crossing logic is essential, along with basic timing closure knowledge. Responsibilities include working on design quality metrics, writing and validating RTL for registers and logic, and potentially owning modules or contributing to top-level integration. Strong problem-solving skills and the ability to work independently or within cross-functional teams are highly valued.