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Lead Analyst-CAE

Salary undisclosed

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Job Description

A Bachelor’s or Higher Degree is the minimum entry required for the position.

Lead Analyst-CAE

  • Skill Set: VLSI Design Verification Debug

About the Role

KEY RESPONSIBILITIES:

  • IOHUB Subsystem test plan creation, DRVR implementation and verification closure.
  • Closely work with Design/Architecture team to develop new verification components in the Testbench.
  • Support SoC to complete IOHUB IPs interoperability testing with external IPs at system level.
  • Attend conference call for status sync up with global team.

PREFERRED EXPERIENCE:

  • Global company working experience background, fluent oral English.
  • Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.
  • Good knowledge of UVM/Verilog/System C/System Verilog.
  • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques.
  • Knowledge of Fabric and Virtualization is an asset.
  • Scripting languages (Perl, C Shell, Makefile, …) experience.
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