Design Verification Engineer

-Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification. -Create testcase and testbench with UVM methodology -Fullchip/system functional verification, by define verification strategies/methodology​​ and test plan to enable effective verification -Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan -Experience on Emulation will be an add on. Qualification: -MS plus 6+ years or BS plus 8+ years of experience with complex ASIC designs and/or verification. -Pre-silicon system verification experiences in the areas of SoC, FPGA and embedded microprocessor design verification are strong pluses. -Familiar with System Verilog, UVM and strong programming skills in scripting or C. -Previous experiences in constraint random verification using UVM/System Verilog and coverage driven verification would be the required skill sets. -Familiar with Gate Level Simulation (GLS) and/or Unified Power Format (UPF) would have the advantages.