FPGA Silicon Design Engineer

-Part of the global PCIe/CXL Center of Excellent (CoE) team, developing the latest & state of the art PCIe/CXL solution for next generation FPGA in the latest process technology node. -Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. -Participates in the definition of PCIe/CXL architecture and microarchitecture features of the block being designed. Works with IP providers to integrate and validate IPs at the SoC level. -Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. -Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. -Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. -Drives quality assurance compliance for smooth IP/SoC handoff. Qualification: -Bachelor’s degree in electrical/computer engineering or related field and 7+ years of experience Or a master’s degree in electrical/computer engineering or related field and 6+ years of experience. -Experience in micro-architecture (clocking, reset, power, etc) definition & debug. Good knowledge of PCIe/CXL or high-speed serial interface protocol, such as USB or Ethernet. 5+ years of RTL coding and/or IP integration experience into SoC design. -Experience in design related tools such as LINT, CDC, PT-STA, Fishtail, Power UPF etc & design concept such as data flow, algorithm state machine, finite state machines, and timing charts. -Knowledge on FPGA background would be a plus. -Highly motivated individual, team player with good communication skill.