DFT Design Engineer

-Contribute to high-level DFD architecture specification, work with IP sub-system designers to implement design for debug features and standardize interfaces, integrate and validate full-chip DFD network. -Build DFD capability, through technical coaching to junior engineers. -Work collaboratively with the DFD architect, the design partners and post-silicon validation engineers to implement innovative and robust DFD solutions to Altera FPGA product families. Qualification: -Bachelor or Master in Electrical/Electronics/Computer Engineering or related field. -Good understanding of the ASIC design flow as well as the design for debug requirements. -Familiar with digital design and integration, various validation techniques and industry standard methodologies – JTAG, IJTAG, BSCAN, BIST, etc. -Proficiency in scripting languages such as TCL/TK/PERL/Python. Preferred Qualifications: -In depth understanding of the latest industry DFD tools and methodology, and have experienced to innovatively adapt those technology to specific product needs. -Direct experience in complex SOC or IP designs and have in-depth understanding of design for debug methodology. The ideal candidate will have the following behavioral traits: -We are looking for an individual who consistently look for ways to do things more efficiently while upholding quality. -Passionate in solving problems, ability to synthesize data and translate into data driven proposals and decisions. -Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.