Senior RTL Design Engineer

Responsible for specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing substantial assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc. -Deep knowledge of mixed signal concepts -Deep knowledge of RTL design fundamentals -Deep knowledge of Verilog and System-Verilog -Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) -Solid understanding of synthesis, static timing, DFT is a huge plus -Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques -Deep knowledge of scripting languages. Perl and Python are plusses -Deep knowledge of Algorithm developments -Strong communication and presentation skills -SERDES knowledge is a plus