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Jobs or company...

Senior Design Verification Engineer

Salary undisclosed
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Company Description:

Sytrons Technology Co., Ltd. is an integrated circuit technology company that provides IP/SOC solution, System customization design solution, Design Service Solutions for customers. Founded in 2009, the company is located in Silicon Valley US and Shanghai, Guangzhou China. The company has grown up to more than 250 employees. With the rapid development of the company, has now set up more branches in the other area as well.

The company has long-term stable suppliers as vendors with the world's top 10 most famous semiconductor design companies such as Broadcom, QUALCOMM, AMD, Marvell, ADI, GF and so on, and also leading edge of the semiconductor companies such as SYNOPSYS, ADI, ALchip, China technology and so on. The company has completed the world's most cutting-edge project and process -40/28/20/16/14/12/10/7/6/5/3n.

Besides, it has completed and participated in the development and design of IP core, chips and products in many fields for customers.

Company unique business model : 1、Provide IP -- IP License Fee/IP Royalty；2、Spec-In solutions，All kinds of IP/SoC, System customization design solution. And cooperative customers development and design chip and product. 3、ASIC design/Customized IC design/Outsouring solutions.

Role Description:

As a Senior Design Verification Engineer (Senior Silicon Design Engineer), you will play a pivotal role in the verification process of IP, contributing to all stages from testbench development to regression debugging. Your responsibilities will include developing test plans, implementing verification methodologies, and enhancing efficiency through script creation. This position requires strong self-drive, excellent communication skills, and adept problem-solving abilities.

Key Responsibilities:

1. Develop and verify new features for IP.

2. Build testbenches and create comprehensive test plans.

3. Debug regressions and ensure the integrity of verification processes.

4. Apply advanced verification methodologies (e.g., UVM, coverage, ASIC design, assertion, randomization) to meet verification goals.

5. Develop scripts to streamline verification processes and enhance efficiency.

Preferred Experience:

1. Proficiency in design for verification techniques, including assertion-based design strategies, code coverage, and functional coverage.

2. Familiarity with PCIE, other IP, or SOC DV.

3. Experience with SystemVerilog (SV) and Universal Verification Methodology (UVM).

4. Comfortable working in a Linux environment.

Required Qualifications:

1. Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.

2. with 3+ years relevant experience with a Bachelor's degree or 2+ years with a Master's degree.

Must have skillset (screening questions):

1. Familiar with PCI Express (PCIE) protocols?

2. Familiar with SystemVerilog(SV) OR Universal Verification Methodology (UVM)?

3. Familiar with Linux Environment?

4. Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan etc

Company Description:

Sytrons Technology Co., Ltd. is an integrated circuit technology company that provides IP/SOC solution, System customization design solution, Design Service Solutions for customers. Founded in 2009, the company is located in Silicon Valley US and Shanghai, Guangzhou China. The company has grown up to more than 250 employees. With the rapid development of the company, has now set up more branches in the other area as well.

The company has long-term stable suppliers as vendors with the world's top 10 most famous semiconductor design companies such as Broadcom, QUALCOMM, AMD, Marvell, ADI, GF and so on, and also leading edge of the semiconductor companies such as SYNOPSYS, ADI, ALchip, China technology and so on. The company has completed the world's most cutting-edge project and process -40/28/20/16/14/12/10/7/6/5/3n.

Besides, it has completed and participated in the development and design of IP core, chips and products in many fields for customers.

Company unique business model : 1、Provide IP -- IP License Fee/IP Royalty；2、Spec-In solutions，All kinds of IP/SoC, System customization design solution. And cooperative customers development and design chip and product. 3、ASIC design/Customized IC design/Outsouring solutions.

Role Description:

As a Senior Design Verification Engineer (Senior Silicon Design Engineer), you will play a pivotal role in the verification process of IP, contributing to all stages from testbench development to regression debugging. Your responsibilities will include developing test plans, implementing verification methodologies, and enhancing efficiency through script creation. This position requires strong self-drive, excellent communication skills, and adept problem-solving abilities.

Key Responsibilities:

1. Develop and verify new features for IP.

2. Build testbenches and create comprehensive test plans.

3. Debug regressions and ensure the integrity of verification processes.

4. Apply advanced verification methodologies (e.g., UVM, coverage, ASIC design, assertion, randomization) to meet verification goals.

5. Develop scripts to streamline verification processes and enhance efficiency.

Preferred Experience:

1. Proficiency in design for verification techniques, including assertion-based design strategies, code coverage, and functional coverage.

2. Familiarity with PCIE, other IP, or SOC DV.

3. Experience with SystemVerilog (SV) and Universal Verification Methodology (UVM).

4. Comfortable working in a Linux environment.

Required Qualifications:

1. Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.

2. with 3+ years relevant experience with a Bachelor's degree or 2+ years with a Master's degree.

Must have skillset (screening questions):

1. Familiar with PCI Express (PCIE) protocols?

2. Familiar with SystemVerilog(SV) OR Universal Verification Methodology (UVM)?

3. Familiar with Linux Environment?

4. Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan etc